A cylindrical gates model of the static induction transistor is proposed and mirror method is used to calculate the distribution of electric potential.The results show that:the potential barrier is directly determined by channel over pinched-off factor;gate efficiency η decreases as the gate dimension α 2 and shifted gate voltage are minished,and what differs from the first-order theory is that η will tend to zero at the shifted gate voltage tends to zero when V D=0;at low current,the voltage amplification factor μ increases as the drain current rising.When the drain current reaches certain degree,the voltage amplification factor keeps almost constant.In the end,an analytical description of SIT’s characteristic suited to both triode-like and mixed I-V characteristics are obtained.The predicted I-V curves are consistent perfectly with the reported experimental ones.
The designing approaches and key fabricating technologies for high frequency high power double dielectrics gate static induction transistor (DDG SIT) with mixed non-saturating I-V characteristics are presented.The effects of parasitic gate-source capacitance (C gs) on the power performance of SIT are discussed.The main methods and considerations to diminish C gs,consequently to improve the high power performance are given.Synchronous epitaxy technology is the critical step to decrease C gs.The 7-μm pitch DDG SIT delivering output power >20W with >7dB power gain and >70% drain efficiency at 400MHz,and delivering output power >7W with >5dB power gain and >50% drain efficiency at 700MHz are successfully fabricated.
Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.
Synchro-epitaxy is introduced and a “two periods epitaxy” process is proposed.The influence of the flows of SiH 4 N 1,N 2,deposition time t 1,t 2,and epitaxial temperature T on epilayer quality (embodied by α) is reported.The shorter initial inducing time t 1 and larger flows of SiH 4 are,the wider single crystal strips are.But the quality of epilayer may be poor.The optimum conditions are:N 1=13.1～17.5sccm,N 2=7.0～7.88sccm,and t 1=30～50s.The influence of temperature is complex:when T is lower than 980℃,single crystal strips increase with T ;when T is higher than 980℃,single crystal strips decrease with T.It reaches maximum near 980℃.
The mixed non-saturating I-V characteristics of static induction transistor (SIT) are investigated.The optimum matching relations among the structural,material,and technological parameters are also presented.The technological experiments demonstrate that the channel parameters play a critical role in determining whether it is a mixed,triode-like or pentode-like I-V characteristics.The general control principles,methods,and criterions of fabrication parameters as well as the effect of control factor are analytically discussed.The results are useful for design and fabrication of SIT,especially for SIT with mixed I-V characteristics.
