提出一种片上网络(NoC)拓扑结构——Spidernet,并对其网络的主要属性如节点度、网络直径、连通度、平均最短路径和平均最短布线等进行了研究。首先将 Spidernet 与其它拓扑结构的属性进行比较,并采用模拟退火的布局映射算法,根据NoC的布局结构,将不同的节点放入 NoC 网格中,即给出一组被绑定和调度的可供选择 IP 核,在满足 IP 核所占用芯片面积的条件下将选择的 IP 核映射到网络中,目标是最小化平均布线长度。网络拓扑结构图描述文件和 IP 核任务图作为输入。实验中运行基准程序,结果表明提出的网络拓扑结构更适合于将来的 SoC 的片上网络构造。
To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.
