This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter （ADC） based on an improved 1.5bit/stage architecture. The ADC achieves a peak signal-to-noise-and-distortion ratio （SNDR） of 57dB and maintains 51dB up to 57MHz, the Nyquist frequency for a clock rate of 100Msample/s. The differential non-linearity （DNL） and integral non-linearity （INL） are typically measured as 0.3LSB and 1.0LSB, respectively. The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm^2.
