We investigate the negative bias temperature instability （NBTI） of 90nm pMOSFETs under various temperatures and stress gate voltages （Vg）. We also study models of the time （t） ,temperature （T） ,and stress Vg dependence of 90nm pMOSFETs NBTI degradation. The time model and temperature model are similar to previ- ous studies, with small difference in the key coefficients. A power-law model is found to hold for Vg, which is different from the conventional exponential Vg model. The new model is more predictive than the exponential model when taking lower stress Vg into account.
A combination of atomic force microscopy （AFM） and scanning electron microscopy （SEM） is used to characterize dislocation etch pits in Si-doped GaN epilayer etched by molten KOH. Three types of etch pits with different shapes and specific positions in the surface have been observed,and a model of the etching mechanism is proposed to explain their origins. The pure screw dislocation is easily etched along the steps that the dislocation terminates. Consequently a small Ga-polar plane is formed to prevent further vertical etching,resulting in an etch pit shaped like an inverted truncated hexagonal pyramid at the terminal chiasma of two surface steps. However, the pure edge dislocation is easily etched along the dislocation line,inducing an etch pit of inverted hexagonal pyramid aligned with the surface step. The polarity is found to play an important role in the etching process of GaN.
The reverse generation current under high-gate-voltage stress condition in LDD nMOSFET＇s is studied. We find that the generation current peak decreases as the stress time increases. We ascribe this finding to the dominating oxide trapped electrons that reduce the effective drain bias, lowering the maximal generation rate. The density of the effective trapped electrons affecting the effective drain bias is calculated with our model.
