A programmable multi-modulus frequency divider is designed and implemented in a 0. 35μm CMOS process. The multi-modulus frequency divider is a single chip with two dividers in series,which are divided by 4 or 5 prescaler and by 128-255 multi-modulus frequency divider. In the circuit design, power and speed trade-offs are analyzed for the prescaler, and power optimization techniques are used according to the input frequency of each divider cell for the 128-255 multimodulus frequency divider. The chip is designed with ESD protected I/O PAD. The dividers chain can work as high as 2.4GHz with a single ended input signal and beyond 2.6GHz with differential input signals. The dual-modulus prescaler consumes 11mA of current while the 128-255 multi-modulus frequency divider consumes 17mA of current with a 3.3V power supply. The core area of the die without PAD is 0.65mm × 0.3mm. This programmable multi-modulus frequency divider can be used for 2.4GHz ISM band PLL-based frequency synthesizers. To our knowledge, this is the first reported multi-modulus frequency divider with this structure in China.
This paper demonstrates the design and fabrication of a monolithic HBT power amplifier for TD-SCDMA cellu- lar phones that achieves high efficiency and linearity. The two-stage MMIC integrates the input matching circuits,interstage matching circuits, and active bias circuits in a single chip with size as small as 0.91mm × 0.98mm. The amplifier obtains a power-added efficiency of 43% （15%） and a gain of 28.5dB （24dB） at the high and low operation mode under the 3.4V supply. In addition, the adjacent channel leakage power is below - 45dBc/- 56dBc and - 39dBc/- 50dBc at 1.6MHz/3.2MHz offset in low and high power output modes, respectively, with QPSK modulation. The MMIC offers the potential for low cost production due to small chip size, stable voltage supply, and high performance at the same time.
A monolithic voltage controlled oscillator （VCO） based on negative resistance principle is presented uti-lizing commercially available InGaP/GaAs hetero-junction bipolar transistor （HBT） technology. This VCO is de-signed for 5GHz-band wireless applications. Except for bypass and decoupled capacitors,no external component is needed for real application. Its measured output frequency range is from 4.17 to 4.56GHz,which is very close to the simulation one. And the phase noise at an offset frequency of 1MHz is -112dBc/Hz. The VCO core dissipates 15.5mW from a 3.3V supply,and the output power ranges from 0 to 2dBm. To compare with other oscillators,the figure of merit is calculated,which is about -173.2dBc/Hz. Meanwhile, the principle and design method of nega-tive resistance oscillator are also discussed.
Lattice matched InP based InAlAs/InGaAs HEMTs with 120GHz cutoff frequency are reported.These devices demonstrate excellent DC characteristics:the extrinsic transconductance of 600mS/mm,the threshold voltage of -1 2V,and the maximum current density of 500mA/mm.
An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.
