The paper discusses a new kind of driving the LCD via I/O bus using CPLD and realizing the precise I/Ocontrol timing sequence by establishing the corresponding Verilog-HDL model. The results of application show thatthis solution can not only solve the matching of low-speed device with high-speed bus but also provide the display in-terface during the motherboard debugging process, and also prove that the whole system is reliable and stable.
