A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.
A modular architecture for two dimension (2 D) discrete wavelet transform (DWT) is designed.The image data can be wavelet transformed in real time,and the structure can be easily scaled up to higher levels of DWT.A fast zerotree image coding (FZIC) algorithm is proposed by using a simple sequential scan order and two flag maps.The VLSI structure for FZIC is then presented.By combining 2 D DWT and FZIC,a wavelet image coder is finally designed.The coder is programmed,simulated,synthesized,and successfully verified by ALTERA CPLD.
