A wideband on-chip millimeter-wave patch antenna in 0.18 μm CMOS with a low-resistivity （10 Ω.cm） silicon substrate is presented. The wideband is achieved by reducing the Q factor and exciting the high-order radiation modes with size optimization. The antenna uses an on-chip top layer metal as the patch and a probe station as the ground plane. The on-chip ground plane is connected to the probe station using the inner connection structure of the probe station for better performance. The simulated S11 is less than -10 dB over 46-95 GHz, which is well matched with the measured results over the available 40-67 GHz frequency range from our measurement equipment. A maximum gain of-5.55 dBi with 4% radiation efficiency at a 60 GHz point is also achieved based on Ansofi HFSS simulation. Compared with the current state-of-the-art devices, the presented antenna achieves a wider bandwidth and could be used in wideband millimeter-wave communication and image applications.
A 40-GHz phase-locked loop（PLL） frequency synthesizer for 60-GHz wireless communication applications is presented. The electrical characteristics of the passive components in the VCO and LO buffers are accurately extracted with an electromagnetic simulator HFSS. A differential tuning technique is utilized in the voltage controlled oscillator（VCO） to achieve higher common-mode noise rejection and better phase noise performance. The VCO and the divider chain are powered by a 1.0 V supply while the phase-frequency detector（PFD）and the charge pump（CP） are powered by a 2.5 V supply to improve the linearity. The measurement results show that the total frequency locking range of the frequency synthesizer is from 37 to 41 GHz, and the phase noise from a 40 GHz carrier is –97.2 dBc/Hz at 1 MHz offset. Implemented in 65 nm CMOS, the synthesizer consumes a DC power of 62 m W, including all the buffers.
