Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10^(12) cm^(-2),an implant tilt of -2°,a transfer gate channel doping dose of 3.0×10^(12) cm^(-2) and an operation voltage of 3.4 V.The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.
To improve the full well capacity(FWC) of a small size backside illuminated(BSI) CMOS image sensor(CIS),the effect of photodiode capacitance(C_(PD)) on FWC is studied,and a reformed pinned photodiode (PPD) structure is proposed.Two procedures are implemented for the optimization.The first is to form a varying doping concentration and depth stretched new N region,which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region.The FWC of this structure is increased by extending the side wall junctions in the substrate.Secondly,in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region.This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period.The simulation results show that the FWC can be improved from 1289eto 6390e-,and this improvement does not sacrifice any image lag performance.Additionally,quantum efficiency (QE) is enhanced in the full wavelength range,especially 6.3%at 520 nm wavelength.This technique can not only be used in such BSI structures,but also adopted in an FSI pixel with any photodiode-type readout scheme.
A wide-dynamic-range CMOS image sensor(CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion(FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second(fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.
A low reset noise CMOS image sensor(CIS) based on column-level feedback reset is proposed.A feedback loop was formed through an amplifier and a switch.A prototype CMOS image sensor was developed with a 0.18μm CIS process.Through matching the noise bandwidth and the bandwidth of the amplifier,with the falling time period of the reset impulse 6μs,experimental results show the reset noise level can experience up to 25 dB reduction.The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems,especially in low illumination.
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
In order to increase collection efficiency and eliminate image lag,multi n-type implants were introduced into the process of a pinned-photodiode.For the purpose of improving the collection efficiency, multi n-type implants with different implant energies were proposed,which expanded the vertical collection region. To reduce the image lag,a horizontal gradient doping concentration eliminating the potential barrier waalso formed by multi n-type implants.The simulation result shows that the collection efficiency can be improved by about 10%in the long wavelength range and the density of the residual charge is reduced from 2.59×109 to 2.62×107 cm-3.
An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor is presented.This new approach is based on the assumption that the photon shot noise in image signal is impacted by a potential well structure change of pixel.Experimental results show the measured pinch-off voltage is consistent with theoretical prediction.This technique provides an experimental method to assist the optimization of pixel design in both the photodiode structure and fabrication process for the 4-T CMOS image sensor.
A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.
