A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.
A model of monolithic transformers is presented, which is analyzed with characteristic functions. A closed- form analytical approach to extract all the model parameters for the equivalent circuit of Si-based on-chip transformers is proposed. A novel de-coupling technique is first developed to reduce the complexity in the Y parameters for the transformer, and the model parameters can then be extracted analytically by a set of characteristic functions. Simulation based on the extracted parameters has been carried out for transformers with different structures, and good accuracy is obtained compared to a 3-demensional full-wave numerical electro- magnetic field solver. The presented approach will be very useful to provide a scalable and wide-band compact circuit model for Si-based RF transformers.
A wideband receiver RP front-end for IR-UWB applications is implemented in 0.13μm CMOS technology. Thanks to the direct sub-sampling architecture,there is no mixing process.Both LNA and VGA work at RF frequencies.To optimize noise as well as linearity,a differential common-source LNA with capacitive cross- coupling is used,which only consumes current of 1.8 mA from a 1.2 V power supply.Following LNA,a two-stage current-steering VGA is adopted for gain tuning.To extend the overall bandwidth,a three-stage staggered peaking technique is used.Measurement results show that the proposed receiver front-end achieves a gain tuning range from 5 to 40 dB within 6-7 GHz,a minimum noise figure of 4.5 dB and a largest IIP_3 of-11 dBm.The core receiver (without test buffer) consumes 14 mW from a 1.2 V power supply and occupies 0.58 mm^2 area.
A reconfigurable dual-band LNA is presented. The LNA employs switching capacitors and circuit in to realize the dual-band operation. These methodologies are used to design and implement a reconfigurable LNA for IMT-A and UWB application. The LNA is implemented using TSMC-0.13 μm CMOS technology. Measured performance shows an input matching of better than -13.5 dB, a voltage gain of 18-22.8 dB, with an NF of 4.3-4.7 dB in the band of 3.4-3.6 GHz, and an input matching of better than -9.7 dB, a voltage gain of 14.7-22.4 dB, and with an NF of 3.7-4.9 dB in the band of 4.2-4.8 GHz. According to the measure results, the proposed LNA achieves dual-band operation, and it proves the feasibility of the proposed topology.
A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.
This paper presents an LC voltage controlled oscillator（VCO） in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise,power consumption,voltage amplitude,and tuning range.In order to achieve a wide tuning range,a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design.The size of the entire chip with pad is 1.11 0.98 mm2.The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply.The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz.The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz,respectively.
