A passive current switch mixer was designed for the second IF down-conversion in a DRM/DAB re- ceiver. The circuit consists of an input transconductance stage, a passive current switching stage, and a current amplifier stage. The input transconductance stage employs a self-biasing current reusing technique, with a resistor shunt feedback to increase the gain and output impedance. A dynamic bias technique is used in the switching stage to ensure the stability of the overdrive voltage versus the PVT variations. A current shunt feedback is introduced to the conventional low-voltage second-generation fully balanced multi-output current converter （FBMOCCII）, which provides very low input impedance and high output impedance. With the circuit working in current mode, the linearity is effectively improved with low supply voltages. Especially, the transimpedance stage can be re- moved, which simplifies the design considerably. The design is verified with a SMIC 0.18μm RF CMOS process. The measurement results show that the voltage conversation gain is 1.407 dB, the NF is 16.22 dB, and the IIP3 is 4.5 dBm, respectively. The current consumption is 9.30 mA with a supply voltage of 1.8 W. This exhibits a good compromise among the gain, noise, and linearity for the second IF mixer in DRM/DAB receivers.
A limiting amplifier IC implemented in 65nm CMOS technology and intended for high-speed op- tical fiber communications is described in this paper. The inductorless limiting amplifier incorporates 5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance, a high speed output buffer with novel third order active feedback, and a high speed full-wave rectifier. The re- ceiver signal strength indictor （RSSI） can detect input signal power with 33dB dynamic range, and the limiting amplifier features a programmable loss of signal （LOS） indication with external resistor. The sensitivity of the limiting amplifier is 5.5mV at BER = 10^ -12 and the layout area is only 0.53 × 0.72 mm^2 because of no passive inductor. The total gain is over 41dB, and bandwidth exceeds 12GHz with 56mW power dissipation.
A novel 10 GHz eight-phase voltage-controlled oscillator （VCO） architecture applied in clock and data recovery （CDR） circuit for 40 Gbit/s optical communications system is proposed. Compared with the traditional eight-phase oscillator, a new ring CL ladder filter structure with four inductors is proposed. The VCO is designed and fabricated in IBM 90 nm complementary metal-oxide-semiconductor transistor （CMOS） technology. Measurement results show the tuning range is 9.2 GHz-11.0 GHz and the phase noise of - 108.85 dBc/Hz at 1 MHz offset from the carrier frequency of 10 GHz. The chip area of VCO is 500 μm × 685 μm and the power dissipation is 17.4 mW with the 1.2 V supply voltage.
Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
