A 0.8–4.2 GHz monolithic all-digital PLL based frequency synthesizer for wireless communications is successfully realized by the 130 nm CMOS process. A series of novel methods are proposed in this paper.Two band DCOs with high frequency resolution are utilized to cover the frequency band of interest, which is as wide as 2.5 to 5 GHz. An overflow counter is proposed to prevent the ＂pulse-swallowing＂ phenomenon so as to significantly reduce the locking time. A NTW-clamp digital module is also proposed to prevent the overflow of the loop control word. A modified programmable divider is presented to prevent the failure operation at the boundary.The measurement results show that the output frequency range of this frequency synthesizer is 0.8–4.2 GHz. The locking time achieves a reduction of 84% at 2.68 GHz. The best in-band and out-band phase noise performances have reached –100 d Bc/Hz, and –125 d Bc/Hz respectively. The lowest reference spur is –58 d Bc.
A novel transformer-type variable inductor is proposed to achieve a wide tuning range at frequencies as high as K band. The variable inductor is designed, and an intuitive model is built to analyze its performance by HFSS. A lot of mathematical analysis is done in detail. A VCO using the proposed variable inductor is designed with TSMC 0.13 μm CMOS technology for verification. The frequency tuning range of the VCO depends on the proposed variable inductor. The phase noise of the VCO depends on the quality of the LC tank （including the proposed variable inductor and varactors）. So a specific AMOS varactor is implemented to improve its quality factor. The VCO is simulated at three typical TSMC fabrication comers （TT, FF, SS） to predict its measure results. The post simulation results shows that the VCO achieves a 20-25.5 GHz continuous tuning range. Its phase noise results at 1 MHz offset are -108.4 dBc/Hz and -100.5 dBc/Hz respectively at the tuning frequencies of 19.6 GHz and 25.5 GHz. The VCO draws only 3 to 6 mA from a 1.2 V power supply.
