The retention characteristics of electrons and holes in hafnium oxide with post-deposition annealing in a N2 or 02 ambient were investigated by Kelvin probe force microscopy. The KFM results show that compared with the N2 PDA process, the O2 PDA process can lead to a significant retention improvement. Vertical charge leakage and lateral charge spreading both played an important role in the charge loss mechanisms. The retention improvement is attributed to the deeper trap energy. For electrons, the trap energy of the HOS structure annealed in a N2 or 02 ambient were determined to be about 0.44 and 0.49 eV, respectively. For holes, these are about 0.34 and 0.36 eV, respectively. Finally, the electrical characteristics of the memory devices are demonstrated from the experiment, which agreed with our characterization results. The qualitative and quantitative determination of the charge retention properties, the possible charge decay mechanism and trap energy reported in this work can be very useful for the characterization of hafnium charge storage devices.
We have investigated the effect of post deposition annealing (PDA) temperature of Al2O3 blocking layer on the performance of charge trapping memory capacitors. Two splits of PDA were performed in N2 ambient at 850°C/60 s and 1050°C/60 s, respectively. The 1050°C annealed capacitor could be programmed and erased normally by using Fowler-Nordheim (FN) injection. In contrast, the 850°C annealed device could not be erased, even though it could be programmed properly. By measuring the gate leakage current and the flatband voltage shift, we found the erase failure in the 850°C annealed device was due to a larger gate back-injection leakage current at Vg<0. The trend of gate leakage current was further verified in two Al/Al2O3/SiO2/p-Si control capacitors with the same PDA splits. In addition, constant voltage stress measurements on control capacitors in the FN regime showed that the change of gate leakage current followed an empirical Curie-von Schweidler law at Vg<0. The data pointed out the importance to further study the relation between PDA conditions and the defect generation properties in Al2O3 blocking layer.
JIN LinZHANG ManHongHUO ZongLiangYU ZhaoAnJIANG DanDanWANG YongBAI JieCHEN JunNingLIU Ming
This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.
This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3 D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.
With the merits of a simple process and a short fabrication period, the capacitor structure provides a convenient way to evaluate memory characteristics of charge trap memory devices. However, the slow minority carrier generation in a capacitor often makes an underestimation of the program/erase speed. In this paper, illumination around a memory capacitor is proposed to enhance the generation of minority carriers so that an accurate measurement of the program/erase speed can be achieved. From the dependence of the inversion capacitance on frequency, a time constant is extracted to quantitatively characterize the formation of the inversion layer. Experimental results show that under a high enough illumination, this time constant is greatly reduced and the measured minority carrier-related program/erase speed is in agreement with the reported value in a transistor structure.
