A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming （MLP） problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.
A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.
We propose a novel thermal-conscious power model for integrated circuits that can accurately predict power and temperature under voltage scaling. Experimental results show that the leakage power consumption is underestimated by 52 % if thermal effects are omitted. Furthermore, an inconsistency arises when energy and temperature are simultaneously optimized by dynamic voltage scaling. Temperature is a limiting factor for future integrated circuits,and the thermal optimization approach can attain a temperature reduction of up to 12℃ with less than 1.8% energy penalty compared with the energy optimization one.
