This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.
The impacts ofsubstrate parasitic resistance and drain ballast resistance on electrostatic discharge （ESD） robustness of LDMOS are analyzed. By increasing the two parasitic resistances, the ESD robustness of LDMOS are significantly improved. The proposed structures have been successfully verified in a 0.35μm BCD process without using additional process steps. Experimental results show that the second breakdown current of the optimal structure increases to 3,5 A, which is about 367% of the original device.
A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mf2.cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.
Criterion for the second snapback of an LDMOS with an embedded SCR is given based on parasitic parameter analysis.According to this criterion,three typical structures are compared by numerical simulation and structural parameters which influence the second snapback are also analyzed to optimize the ESD characteristics. Experimental data showed that,as the second snapback voltage decreased from 25.4 to 8.1 V,the discharge ability of the optimized structure increased from 0.57 to 3.1 A.
A thick SOI LIGBT structure with a combination of uniform and variation in lateral doping profiles （UVLD） on partial membrane （UVLD PM LIGBT） is proposed. The silicon substrate under the drift region is selectively etched to remove the charge beneath the buried oxide so that the potential lines can release below the membrane, resulting in an enhanced breakdown voltage. Moreover, the thick SOI LIGBT with the advantage of a large current flowing and a thermal diffusing area achieves a strong current carrying capability and a low junction temperature. The current carrying capability （VAnode = 6 V, VGate = 15 V） increases by 16% and the maximal junction temperature （1 mW/μm） decreases by 30 K in comparison with that of a conventional thin SO1 structure.
A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ.cm^2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.
