A low power high performance Delta-Sigma modulator for portable measurement applications is presented. To reduce power consumption while maintaining high performance, a fully feedforward architecture with a comprehensive system-level design is implemented. As a key building block, a novel power efficient current mirror operational transconductance amplifier (OTA) with a fast-settling less-error switched-capacitor common-mode feedback (SC CMFB) circuit is introduced, and the effects of both gain nonlinearity and 1/f noise of OTA are discussed. A new method to determine the voltage gain of an OTA is also proposed. The bottom terminal parasitic effect of poly-insulator-poly (PIP) capacitors is considered. About an extra 20% of capacitance is added to the total capacitance load. A power and area efficient resonator is adopted to realize a coefficient of 1/90 for 50% power and 75% area reduction compared with conventional designs. The chip is implemented in a low cost 0.35 μm complementary metal oxide semiconductor (CMOS) process. The total power consumption is 20 μW with a 1.5 V supply, and the measured dynamic range (DR) is 95 dB over a 1 kHz bandwidth. Experimental results show that a high figure-of-merit (FOM) is achieved for the designed modulator in comparison with those from the literature.
This paper presents a low-power high-precision switched-opamp（SO）-based delta-sigma（△Σ） analog-to -digital converter（ADC）.The proposed SO design allows circuit operation at sub-1 V supply voltage,only needs to work in half of a clock cycle,and thus is suitable for low power applications.In addition,an opamp-sharing technique is applied to save on hardware overheads.Due to the use of a dual cycle shift data weighted averaging （DCS-DWA） technique,mismatch errors caused in the feedback DAC have been eliminated without introducing signal-dependent tones.The proposed ADC has been implemented in a standard 0.18μm process and measured to have a 92.2 dB peak SNDR and 94.1 dB dynamic range with 25 kHz signal bandwidth.The power consumption is 58μW for the modulator at 0.9 V supply voltage and 96μW for the decimation filter,which translate to the figure-of-merit（FOM） of 35.4 fJ/step for the solo modulator,and 94 fJ/step for the whole system.
An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output（SIDO） buck converter in pseudo-continuous conduction mode（PCCM） with a self-adaptive freewheeling current level（SFCL） is presented.Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter.Moreover,an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers.Instead of keeping it as a constant value,the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time.To verify the feasibility of the proposed controller,an SIDO buck converter with two regulated output voltages,1.8 V and 3.3 V,is designed and fabricated in HEJIAN 0.35 m CMOS process.Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 s while the cross-regulation is reduced to 0.057 mV/mA,when its first load changes from 50 to 100 mA.
