This paper presents a CMOS G;-C complex filter for a low-IF receiver of the IEEE802.15.4 standard.A pseudo differential OTA with reconfigurable common mode feedback and common mode feed-forward is proposed as well as the frequency tuning method based on a relaxation oscillator.A detailed analysis of non-ideality of the OTA and the frequency tuning method is elaborated.The analysis and measurement results have shown that the center frequency of the complex filter could be tuned accurately.The chip was fabricated in a standard 0.35μm CMOS process,with a single 3.3 V power supply.The filter consumes 2.1 mA current,has a measured in-band group delay ripple of less than 0.16μs and an IRR larger than 28 dB at 2 MHz apart,which could meet the requirements of the IEEE802.15.4 standard.
A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC（automatic gain control） and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL（sound pressure level）.Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power（48μW at 1.4 V） can be easily achieved in a high threshold-voltage CMOS process of 0.35μm（V（TON） ＋ ｜V（TOP）｜≈1.35 V）.The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm^2 and 1×1 mm^2.
A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.
A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.
A hearing aid on-chip system based on accuracy optimized front- and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front-andback-endblocks,respectively,soastoalleviatethenonlinearitydistortioncausedbytheoutputswing.By usingthetechnique,theaccuracyofthewholehearingaidsystemcanbesignificantlyimproved.Theprototypechip has been designed with a 0.13 m standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 loudspeaker with a normalized output level of 300 mV p-p, the total harmonic distortion reached about60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 υV rms.
