An improved trench gate super-junction insulated-gate bipolar transistor is presented. The improved structure contains two emitter regions. The first emitter region of the device works as the conventional structure,which can absorb both the electron current and hole current. The second emitter on the top of the p-pillar acts as the hole current diverter, leading to an improved latch-up capability without sacrificing the off-state breakdown voltage(BV) and turn-off loss. The simulation shows that the latch-up limit of the SJ-IGBT increases from 15000 to 28300 A/cm2 at VGE D10 V, the BV is 810 V, and the turn off loss is 6.5 m J/cm2 at Von D1.2 V.
The ESD response characteristic in a p-type symmetric lateral DMOS(ps-LDMOS) has been investigated. The experimental results show that the ps-LDMOS has weak ESD robustness due to an absence of the"snapback" characteristic. In addition, the location of the hot spot changes little for the special device. The method for reducing the lattice temperature of the hot spot can be used to enhance the ESD capacity of the ps-LDMOS,thereby, a novel and easily-achievable ps-LDMOS structure with a p-type lightly doped drain(p-LDD) has been proposed. The special region p-LDD lowers the electric field at the edge of the poly gate, making the whole distribution of the surface electric field more uniform. Therefore, the ESD robustness is improved two times and no obvious change of other electric parameters is introduced.
