A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
该文针对片上网络提出一种基于提前分配路径的低时延片上路由器结构(PAPR)。新路由器采用提前路由计算和提前分配路径来缩短路由器流水线深度。提前路由计算为虚信道提前分配提供了可靠保障,即使在虚信道路径提前分配失败的情况下,也不影响分组在网络中的传输时延。该文提出基于缓存状态的仲裁算法BSTS(BufferStatus)综合考虑当前节点缓存信息和下游节点缓存信息,不但降低了分组等待时延,而且降低了缓存空闲的概率。仿真结果表明,新路由器能明显改善网络的时延和吞吐性能,相比采用滑动迭代轮询仲裁iSLIP(iterativeRound-Robin Matching with SLIP(Serial Line Interface Protocal))算法的经典虚信道路由器,网络平均端到端时延降低了24.5%,吞吐率提高了27.5%;与采用轮询迭代RRM(Round-Robin Matching)算法的经典虚信道路由器相比,平均端到端时延降低了39.2%,吞吐率提高了47.2%。路由器硬件开销和平均功耗分别增加仅为8.9%,5.9%。
