In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si (110) nanowire via the simulation of strain distribution and the calculation of a generalized 6×6k·p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO 2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO 2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO 2 insulator, the strain of the HfO 2 gate insulator in Si (110) nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO 2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.
The Monte Carlo simulation is performed to investigate the quantum mechanical (QM) effects on heat generation in nano-scale metal oxide semiconductor field effect transistors (MOSFETs) by solving the quantum Boltzmann equation. The influence of QM effects both in real space and K space on the heat generation is investigated.
Interface roughness strongly influences the performance of germanium metal-organic-semiconductor field effect transistors(MOSFETs).In this paper,a 2D full-band Monte Carlo simulator is used to study the impact of interface roughness scattering on electron and hole transport properties in long-and short-channel Ge MOSFETs inversion layers.The carrier effective mobility in the channel of Ge MOSFETs and the in non-equilibrium transport properties are investigated.Results show that both electron and hole mobility are strongly influenced by interface roughness scattering.The output curves for 50 nm channel-length double gate n and p Ge MOSFET show that the drive currents of n-and p-Ge MOSFETs have significant improvement compared with that of Si n-and p-MOSFETs with smooth interface between channel and gate dielectric.The 82% and 96% drive current enhancement are obtained for the n-and p-MOSFETs with the completely smooth interface.However,the enhancement decreases sharply with the increase of interface roughness.With the very rough interface,the drive currents of Ge MOSFETs are even less than that of Si MOSFETs.Moreover,the significant velocity overshoot also has been found in Ge MOSFETs.
