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适于纳米尺度集成电路技术的双栅/多栅MOS器件的研究被引量：1: 2008年; 随着集成电路的发展,器件尺寸进入纳米尺度领域,器件性能受到诸多挑战.针对纳米CMOS器件存在的问题,从可集成性考虑,基于由上而下途径,从新型双栅/多栅器件结构角度介绍新型非对称梯度低掺杂漏垂直沟道双栅MOS器件以及新型围栅纳米线MOS器件的研制及特性分析,为下几代集成电路技术的器件研究提供良好的思路.; 黄如田豫周发龙王润声王逸群张兴; 关键词：纳米CMOS器件

Investigations on the Performance Limits of the IMOS Transistor: The Impact Ionization MOS(IMOS) transistor is a kind of promising concept as a candidate of MOS transistor due...; Zhenhua WangRu Huang

SOI DTMOS温度特性研究: 2010年; 对比研究了20μm/0.35μm的SOI（绝缘体上硅）普通MOS和DTMOS（动态阈值MOS）的温度特性。从20-125℃,普通MOS驱动电流减小了12.2%,而DTMOS驱动电流增大了65.3%。SOI DTMOS降低了垂直沟道方向的电场,减少了载流子表面散射,因此阈值电压随温度减小占主导,驱动电流随着温度升高而增大。SOI DTMOS优秀的温度特性,使之非常适合于低压、低功耗、高温应用。; 毕津顺韩郑生海潮和; 关键词：绝缘体上硅温度特性

An Experimental Study on Carrier Transport in Silicon Nanowire Transistors:How Close to the Ballistic Limit?: ＜正＞In this paper,experimental studies on the carrier transport in silicon nanowire transistors（SNWTs） are repo...; Runsheng WangJing ZhugeRu HuangLiangliang ZhangDong-Won KimXing ZhangDonggun ParkYangyuan Wang; 文献传递

Challenges of 22 nm and beyond CMOS technology被引量：8: 2009年; It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate （HK/MG） stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.; HUANG RuWU HanMingKANG JinFengXIAO DeYuanSHI XueLongAN XiaTIAN YuWANG RunShengZHANG LiangLiangZHANG XingWANG YangYuan

Investigations on Proton-Irradiation-Induced Spacer Damage in Deep-Submicron MOSFETs: In this paper,we have focused our attention on DC characteristics degradation of 0.18μm MOSFETs after 10-MeV p...; Shoubin XuePengfei WangRu HuangDake WuYunpeng PeiWenhua WangXing Zhang

Investigation of the RESURF Dielectric Inserted (REDI) LDMOS as a novel Silicon-based RF Power Device: In this paper,a novel power device named as RESURF Dielectric Inserted(REDI) LDMOS is put forward.It is fully ...; Yuchao LiuHan XiaoRu Huang

Investigations on the Physical Understanding of Mobility in MOSFETs——from Drift-Diffusion to Quasi-Ballistic: This paper provides scattering matrix method to analyze the transport property in nanoscale MOSFETs.A unified ...; Hongwei LiuRunsheng WangRu HuangXing Zhang

130nm PDSOI DTMOS体延迟研究: 2010年; 研究了基于IBM 8RF 130 nm工艺部分耗尽绝缘体上Si(PDSOI)动态阈值晶体管(DTMOS)体电阻、体电容以及体电阻和体电容乘积(体延迟)随Si膜厚度和器件宽度的变化。结果表明,Si膜厚度减小会导致体阻增大、体电容减小,但是体电阻和体电容的乘积却明显增大。Si膜厚度从200 nm减小到80 nm,体延迟增加将近两个数量级。器件宽度增加使得体电阻和体电容都明显增大,DTMOS电路延迟也因此指数递增。推导出了PDSOI DTMOS的延迟模型,为SOI DTMOS器件设计提供了参考。; 毕津顺韩郑生海潮和; 关键词：体电阻

一维GaN纳米结构的制备、表征及其特性研究: 2008年; 采用在石英炉中,氨化Ga2O3薄膜的方法,在Si(111)衬底上成功了制备GaN纳米结构薄膜:纳米线、纳米棒.分别用X射线衍射仪(XRD,Rigaku D/Max-rB Cu Kα)、傅立叶红外透射谱(FTIR,TENSOR27)、扫描电子显微镜(SEM,Hitachi S-570)、高分辨电镜(HRTEM,Philips TECNAI F30)和光致发光谱对样品的结构、成分、形貌和光学特性进行了测量分析.最后,简要的讨论了其生长机制.; 薛守斌张兴庄惠照薛成山; 关键词：磁控溅射

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国家重点基础研究发展计划(2006CB302701)