The prototype of a time digitizing system for the BESⅢ endcap TOF （ETOF） upgrade is introduced in this paper, The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber （MRPC） are signaled as LVDS by front-end electronics （FEE） and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module （TDIG） of this prototype can support up to 72 electrical channels for hit information measurement. The fast control （FCTL） module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF （BTOF） structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.
Due to the large scale of Water Cherenkov Detector Array in Large High Altitude Air Shower Observatory, the frontend digitization is imperative.Thus a clock distribution system is desired,which broadcasts the synchronous clock signals with low jitter to the frontend electronics distributed in the field of 90 000 m^2.The White Rabbit protocol provides an option,which has been approved to achieve sub-ns accuracy and ps jitter in the synchronization of around 1 000 nodes in the order of 10 km.But the hierarchy of the original is too complex for Large High Altitude Air Shower Observatory application.Thus we proposed a reduced scheme based on the White Rabbit protocol.The validation circuit shows that the clock skew due to the fiber length difference can be adjusted to less than 25 ps and the clock jitter is less than 62 ps.
An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
The LHAASO （Large High Altitude Air Shower Observatory） experiment is proposed for a very high energy gamma ray source survey, in which the WCDA （Water Cherellkov Detector Array） is one of the major coinponents. In the WCDA, a total of 3600 PMTs are placed under water in four ponds, each with a size of 150m×150 m. Precise time and cimrge measurement is required for the PMT signals, over a large signal amplitude range from a single P.E. （photo electron） to 4000 P.E. To fulfill the high requirement of a signal measurement in so many front end nodes scattered in a large area, special techniques are developed, such as multiple gain readout, hybrid transmission of clocks, commands and data, precise clock phase alignment and new trigger electronics. We present the readout electronics architecture for the WCDA and several prototype modules, which are now being testedin the laboratory.
For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.
The Large Area Water Cherenkov Array （LAWCA） experiment focuses on high energy gamma astronomy between 100 GeV and 30 TeV. Invoked by the idea of hardware triggerless structure, a prototype of LAWCA trigger electronics is implemented in one single VME-9U module which obtains all the data from the 100 Front End Electronic （FEE） endpoints. Since the trigger electronics accumulate all the information, the flexibility of trigger processing can be improved. Meanwhile, the dedicated hardware trigger signals which are fed back to front end are eliminated; this leads to a system with better simplicity and stability. To accommodate the 5.4 Gbps system average data rate, the fiber based high speed serial data transmission is adopted. Based on the logic design in one single FPGA device, real-time trigger processing is achieved; the reprogrammable feature of the FPGA device renders a reconfigurable structure of trigger electronics. Simulation and initial testing results indicate that the trigger electronics prototype functions well.
Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer（PHY） is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission.This kind of data path is fully implemented by hardware. From the side of the data acquisition system（DAQ）,however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented.Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner.
With increasing physical event rates and the number of electronic channels, traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane. In this paper, a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ. Features of explicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments. Furthermore,to guarantee the readout performance and flexibility, a standalone embedded CPU system is utilized for network protocol stack processing. To receive the customized data format and protocol from front-end electronics, a field programmable gate array（FPGA） is used for logic reconfiguration. To optimize the interface and to improve the data throughput between CPU and FPGA, a sophisticated method based on SRAM is presented in this paper. For the purpose of evaluating this high-speed readout method, a simplified readout module is designed and implemented.Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.
