In this paper,ground-signal-ground type through-silicon vias（TSVs） exploiting air gaps as insulation layers are designed,analyzed and simulated for applications in millimeter wave.The compact wideband equivalent-circuit model and passive elements（RLGC） parameters based on the physical parameters are presented with the frequency up to 100 GHz.The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm.Therefore,the applied voltage of TSVs only needs to achieve the flatband voltage,and there is no need to indicate the threshold voltage.This is due to the small permittivity of air gaps.The proposed model shows good agreement with the simulation results of ADS and Ansoft＇s HFSS over a wide frequency range.
Through-silicon-via （TSV） to TSV crosstalk noise is one of the key factors affecting the signal integrity of three- dimensional integrated circuits （3D ICs）. Based on the frequency dependent equivalent electrical parameters for the TSV channel, an analytical crosstalk noise model is established to capture the TSV induced crosstalk noise. The impact of various design parameters including insulation dielectric, via pitch, via height, silicon conductivity, and terminal impedance on the crosstalk noise is analyzed with the proposed model. Two approaches are proposed to alleviate the TSV noise, namely, driver sizing and via shielding, and the SPICE results show 241 rnV and 379 mV reductions in the peak noise voltage, respectively.
Based on the complex effective conductivity method, a closed-form expression for the internal impedance of mixed carbon nanotube （CNT） bundles, in which the number of CNTs for a given diameter follows a Gaussian distribution, is proposed in this paper. It can appropriately capture the skin effect as well as the temperature effect of mixed CNT bundles. The results of the closed-form expression and the numerical calculation are compared with various mean diameters, standard deviations, and temperatures. It is shown that the proposed model has very high accuracy in the whole frequency range considered, with maximum errors of 1% and 2.3% for the resistance and the internal inductance, respectively. Moreover, by using the proposed model, the high-frequency electrical characteristics of mixed CNT bundles are deeply analyzed to provide helpful design guidelines for their application in future high-performance three-dimensional integrated circuits.
The bufferless router emerges as an interesting option for cost-efficient in network-on-chip （NoC） de- sign. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router （LBBDR） for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle iden- tifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits con- tend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.
The design of a router in a network-on-chip （NoC） system has an important impact on some perfor- mance criteria. In this paper, we propose a low overhead load balancing router （LOLBR） for 2D mesh NoC to enhance routing performance criteria with low hardware overhead. The proposed LOLBR employs a balance tog- gle identifier to control the initial routing direction of X or Y for flit injection. The simplified demultiplexers and multiplexers are used to handle output ports allocation and contention, which provide a guarantee of deadlock avoidance. Simulation results show that the proposed LOLBR yields an improvement of routing performance over the reported routing schemes in average packet latency by 26.5%. The layout area and power consumption of the network compared with the reported routing schemes are 15.3% and 11.6% less respectively.
