This paper describes a new method to create nanoscale SiO2 pits or channels using single-walled carbon nanotubes （SWNTs） in an HF solution at room temperature within a few seconds. Using aligned SWNT arrays, a pattern of nanoscale SiO2 channels can be prepared. The nanoscale SiO2 patterns can also be created on the surface of three- dimensional （3D） SiO2 substrate and even the nanoscale trenches can be constructed with arbitrary shapes. A possible mechanism for this enhanced etching of SiO2 has been qualitatively analysed using defects in SWNTs, combined with H3O＋ electric double layers around SWNTs in an HF solution.
The via interconnects are key components in ultra-large scale integrated circuits （ULSI）. This paper deals with a new method to create single-walled carbon nanotubes （SWNTs） via interconnects using alternating dielectrophoresis （DEP）. Carbon nanotubes are vertically assembled in the microscale via-holes successfully at room temperature under ambient condition. The electrical evaluation of the SWNT vias reveals that our DEP assembly technique is highly reliable and the success rate of assembly can be as high as 90%. We also propose and test possible approaches to reducing the contact resistance between CNT vias and metal electrodes.
