The fabrication and characterization of strained-Si material grown on a relaxed Si0.79 Ge0.21/graded Si1-x- Gex/Si virtual substrate, using reduced pressure chemical vapor deposition, are presented. The Ge concentration of the constant composition SiGe layer and the grading rate of the graded SiGe layer are estimated with double-crystal X-ray diffraction and further confirmed by SIMS measurements. The surface root mean square roughness of the strained Si cap layer is 2.36nm,and the strain is about 0.83% as determined by atomic force microscopy and Raman spectra, respectively. The threading dislocation density is on the order of 4 × 10^4cm^-2. Furthermore, it is found that the stress in the strained Si cap layer is maintained even after the high thermal budget process, nMOSFET devices are fabricated and measured in strained-Si and unstrained bulk-Si channels. Compared to the co-processed bulk-Si MOSFETs at room temperature,a significant low vertical field mobility enhancement of about 85% is observed in the strained-Si devices.
The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate s
Xinhua Zhu Jian-min Zhu Aidong Li Zhiguo Liu Naiben Ming
Biaxial strain technology is a promising way to improve the mobility of both electrons and holes, while （100） channel direction appears as to be an effective booster of hole mobility in particular. In this work, the impact of biaxial strain together with （100） channel orientation on hole mobility is explored. The biaxial strain was incorporated by the growth of a relaxed SiGe buffer layer,serving as the template for depositing a Si layer in a state of biaxial tensile strain. The channel orientation was implemented with a 45^o rotated design in the device layout,which changed the channel direction from （110） to （100） on Si （001） surface. The maximum hole mobility is enhanced by 30% due to the change of channel direction from （110） to （100） on the same strained Si （s-Si） p-MOSFETs,in addition to the mobility enhancement of 130% when comparing s-Si pMOS to bulk Si pMOS both along （110） channels. Discussion and analysis are presented about the origin of the mobility enhancement by channel orientation along with biaxial strain in this work.
(ZrO2)x(SiO2)1-x (Zr-Si-O) films with different compositions were deposited on p-Si(100) substrates by using pulsed laser deposition technique. X-ray photoelectron spectra (XPS) showed that these films remained amorphous after annealing at 800℃ with RTA process in N2 for 60 s. The XPS spectra indi- cated that Zr-Si-O films with x=0.5 suffered no obvious phase separation after annealing at 800℃, and no interface layer was formed between Zr-Si-O film and Si substrate. While Zr-Si-O films with x >0.5 suffered phase separation to precipitate ZrO2 after annealing under the same condition, and SiO2 was formed at the interface. To get a good interface between Zr-Si-O films and Si substrate, Zr-Si-O films with bi-layer structure (ZrO2)0.7(SiO2)0.3/(ZrO2)0.5(SiO2)0.5/Si was deposited. The electrical properties showed that the bi-layer Zr-Si-O film is of the lowest equivalent oxide thickness and good interface with Si substrate.
Lü ShiCheng1,2, YIN Jiang1,2, XIA YiDong2,3, GAO LiGang2,3 & LIU ZhiGuo2,3 1 Department of Physics, Nanjing University, Nanjing 210093, China
High quality strain-relaxed thin SiGe virtual substrates have been achieved by combining the misfit strain technique and the point defect technique. The point defects were first injected into the coherently strained SiGe layer through the ＂inserted Si layer＂ by argon ion implantation. After thermal annealing, an in- termediate SiGe layer was grown with a strained Si cap layer. The inserted Si layer in the SiGe film serves as the source of the misfit strain and prevents the threading dislocations from propagating into the next epitaxial layer. A strained-SilSiGelinserted-SilSiGe heterostructure was achieved with a threading dislocation density of 1×10^4 cm-2 and a root mean square surface roughness of 0.87 nm. This combined method can effectively fabricate device-quality SiGe virtual substrates with a low threading dislocation density and a smooth surface.
Perovskite ferroelectric nanostructures offer a wide range of functional properties(e.g.,dielectric switchability,piezoelectricity,pyroelectricity,high permittivities and strong electro-optic effects),which have received much attention in theelds of microelectronic devices miniaturization over the last few years.Pronounced size effects of the functional properties have been demonstrated in the perovskite ferroelectric nanostructures.Besides its intrinsic scientic value,fundamental understanding of the size effects in perovskite ferroelectric nanostructures has become critical item for developing a new generation of revolutionary nanodevices.In this article,a comprehensive review of the state-of-the-art research progress on the size effects in perovskite ferroelectric nanostructures which have been achieved from both experiment and theory is provided.It begins with a historical perspective of the size effects in perovskite ferroelectrics,and then highlight the recent progress on the theoretical studies of the size effects in perovskite ferroelectric nanostructures which have been achieved by using different numerical approaches(e.g.,phenomenological approaches,rst-principle computations and the Ising model in a transverseeld).The current progress of the experimental testing of the size effects in perovskite ferroelectric nanostructures(e.g.,nanoparticles,nanowires,nanotubes and nanolms)is summarized.Finally,the perspectives toward the future challenges of the size effects in perovskite ferroelectric nanostructures is reviewed.
