差分功耗分析(Differential Power Analysis,DPA)通过分析密码器件处理不同数据时的功耗差异来盗取密钥。运用具有功耗独立特性的灵敏放大型逻辑(Sense Amplifier Based Logic,SABL)设计密码器件可以有效防御DPA攻击。通过对SABL电路与传统加法器原理的研究,提出了一种能够抗DPA攻击的可重构加法器设计方案。首先,结合SABL电路特点得到具有抗DPA攻击性能的加法器电路;然后利用控制进位方式构成可重构加法器,支持4个8位数据或2个16位数据的加法运算。Spectre模拟验证表明,该加法器逻辑功能正确,与传统加法器相比功耗独立性能提升了97%,防御DPA攻击性能明显。
By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.
By analyzing the principle of process variations, a lightweight Physical Unclonable Function(PUF) circuit based on selectable cross-coupled inverters is proposed in this paper. Firstly, selectable cross-coupled inverters are chosen for two delay paths. Simultaneously, the circuit takes challenge signal to control each delay path. The PUF cell circuit is implemented in Semiconductor Manufacturing International Corporation(SMIC) 65 nm CMOS technology and the layout area is 2.94 mm × 1.68 mm. Then the 64-bit PUF circuit is achieved with the cascade connection of cell circuits. The simulation results show that the randomness is 49.4% and the reliability is 96.5%. Compared to the other works, this PUF circuit improves the encrypt performance and greatly reduces the area.
A novel physical unclonable functions(PUF) circuit is proposed, which relies on non-linear characteristic of analog voltage generated by R–2R ladder DAC. After amplifying the deviation signal, the robustness of the DAC-PUF circuit has increased significantly. The DAC-PUF circuit is designed in TSMC 65 nm CMOS technology and the layout occupies 86.06 63.56 m2. Monte Carlo simulation results show that the reliability of the DAC-PUF circuit is above 98% over a comprehensive range of environmental variation, such as temperature and supply voltage.
