A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed （LFI LDMOS）. A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on- resistance.
A new SOI power device with multi-region high-concentration fixed charge（MHFC） is reported. The MHFC is formed through implanting Cs or I ion into the buried oxide layer（BOX）, by which the high-concentration dynamic electrons and holes are induced at the top and bottom interfaces of BOX. The inversion holes can enhance the vertical electric field and raise the breakdown voltage since the drain bias is mainly generated from the BOX. A model of breakdown voltage is developed, from which the optimal spacing has also been obtained. The numerical results indicate that the breakdown voltage of device proposed is increased by 287% in comparison to that of conventional LDMOS.
A new high-voltage LDMOS with folded drift region （FDR LDMOS） is proposed. The drift region is folded by introducing the interdigital oxide layer in the： Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.
A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges（holes） at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.
