In order to minimize leakage current increase under total ionizing dose(TID) radiation in high density memory circuits,a new isolation technique,combining deep trench isolation(DTI) between the wells,local oxidation of silicon(LOCOS) isolation between the devices within the well,and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator(PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%,and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 m PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation,and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si),with only 50% increase of the active power consumption in read mode.
