本文提出了一个新型的SOI埋层结构SOANN(silicon on aluminum nitride with nothing),用AIN代替传统的SiO2材料,并在SOI埋氧化层中引入空洞散热通道.分析了新结构SOI器件的自加热效应.研究结果表明:用AIN做为SOI埋氧化层的材料,降低了晶格温度,有效抑制了自加热效应.埋氧化层中的空洞,可以进一步提供散热通道,使埋氧化层的介电常数下降,减小了电力线从漏端通过埋氧到源端的耦合,有效抑制了漏致势垒降低DIBL(drain Induced barrier lowering)效应.因此,本文提出的新型SOANN结构可以提高SOI器件的整体性能,具有优良的可靠性.
This paper develops the simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET.The models mainly include the analytical equations of the surface potential,surface electric field and threshold voltage,which are derived by solving two dimensional Poisson equation in strained-Si layer.The models are verified by numerical simulation.Besides offering the physical insight into device physics in the model,the new structure also provides the basic designing guidance for further immunity of short channel effect and draininduced barrier-lowering of CMOS-based devices in nanometre scale.
To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator(SGOI) n-type metal-oxide-semiconductor field-effect transistors(nMOSFETs),this paper proposes a novel device called double step buried oxide(BOX) SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.
Based on the exact resultant solution of two-dimensional Poisson's equation in strained Si and Si1-X GeX layer, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator (SGOI) MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects (SCE), the drain-induced barrier-lowering (DIBL) and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.
On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.
For the first time,a simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully depleted dual-material gate strained-Si-on-insulator(DMG SSOI) MOSFETs is developed.We investigate the improved short channel effect(SCE),hot carrier effect(HCE),drain-induced barrier-lowering(DIBL) and carrier transport efficiency for the novel structure MOSFET.The analytical model takes into account the effects of different metal gate lengths,work functions,the drain bias and Ge mole fraction in the relaxed SiGe buffer.The surface potential in the channel region exhibits a step potential,which can suppress SCE,HCE and DIBL.Also,strained-Si and SOI structure can improve the carrier transport efficiency,with strained-Si being particularly effective.Further, the threshold voltage model correctly predicts a'rollup'in threshold voltage with decreasing channel length ratios or Ge mole fraction in the relaxed SiGe buffer.The validity of the two-dimensional analytical model is verified using numerical simulations.
