A C-band high efficiency and high gain two-stage power amplifier based on Al Ga N/Ga N high electron mobility transistor(HEMT) is designed and measured in this paper. The input and output impedances for the optimum power-added efficiency(PAE) are determined at the fundamental and 2nd harmonic frequency( f0 and 2 f0). The harmonic manipulation networks are designed both in the driver stage and the power stage which manipulate the second harmonic to a very low level within the operating frequency band. Then the inter-stage matching network and the output power combining network are calculated to achieve a low insertion loss. So the PAE and the power gain is greatly improved. In an operation frequency range of 5.4 GHz–5.8 GHz in CW mode, the amplifier delivers a maximum output power of 18.62 W, with a PAE of 55.15% and an associated power gain of 28.7 d B, which is an outstanding performance.
Negative bias temperature instability(NBTI) has become a serious reliability issue, and the interface traps and oxide charges play an important role in the degradation process. In this paper, we study the recovery of NBTI systemically under different conditions in the P-type metal–oxide–semiconductor field effect transistor(PMOSFET), explain the various recovery phenomena, and find the possible processes of the recovery.
Frequency dependent conductance measurements are implemented to investigate the interface states in Al2O3/AlGaN/GaN metal-oxide-semiconductor(MOS) structures. Two types of device structures, namely, the recessed gate structure(RGS) and the normal gate structure(NGS), are studied in the experiment. Interface trap parameters including trap density Dit, trap time constant τit, and trap state energy ETin both devices have been determined. Furthermore,the obtained results demonstrate that the gate recess process can induce extra traps with shallower energy levels at the Al2O3/AlGaN interface due to the damage on the surface of the AlGaN barrier layer resulting from reactive ion etching(RIE).
The effect of the static negative bias temperature(NBT) stress on a p-channel power metal–oxide–semiconductor field-effect transistor(MOSFET) is investigated by experiment and simulation. The time evolution of the negative bias temperature instability(NBTI) degradation has the trend predicted by the reaction–diffusion(R–D) model but with an exaggerated time scale. The phenomena of the flat-roof section are observed under various stress conditions, which can be considered as the dynamic equilibrium phase in the R–D process. Based on the simulated results, the variation of the flat-roof section with the stress condition can be explained.
The degradation produced by hot carrier(HC) in ultra-deep sub-micron n-channel metal oxide semiconductor field effect transistor(nMOSFET) has been analyzed in this paper. The generation of negatively charged interface states is the predominant mechanism for the ultra-deep sub-micron nMOSFET. According to our lifetime model of p-channel MOFET(pMOFET) that was reported in a previous publication, a lifetime prediction model for nMOSFET is presented and the parameters in the model are extracted. For the first time, the lifetime models of nMOFET and pMOSFET are unified. In addition, the model can precisely predict the lifetime of the ultra-deep sub-micron nMOSFET and pMOSFET.
The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W ), channel length (L), and stress voltage (Vd ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.
