The change of P+ deep well doping will affect the charge collection of the active and passive devices in nano-technology,thus affecting the propagated single event transient(SET) pulsewidths in circuits.The propagated SET pulsewidths can be quenched by reducing the doping of P+ deep well in the appropriate range.The study shows that the doping of P+ deep well mainly affects the bipolar amplification component of SET current,and that changing the P+ deep well doping has little effect on NMOS but great effect on PMOS.
An analytical model is proposed to calculate single event transient (SET) pulse width with bulk complementary metal oxide semiconductor (CMOS) technology based on the physics of semiconductor devices. Combining with the most prevalent negative bias temperature instability (NBTI) degradation model, a novel analytical model is developed to predict the time evolution of the NBTI induced SET broadening in the production, and NBTI experiments and three-dimensional numerical device simulations are used to verify the model. At the same time, an analytical model to predict the time evolution of the NBTI induced SET broadening in the propagation is also proposed, and NBTI experiments and the simulation program with integrated circuit emphasis (SPICE) are used to verify the proposed model.
A novel off-state gate RHBD technique to mitigate the single-event transient(SET)in the differential data path of analog circuit is demonstrated in this paper.Simulation results present that this off-state gate technique could exploit charge sharing in differential circuits and reduce differential mode voltage perturbation effectively.It is indicated that this technique is more effective to mitigate SET than the differential charge cancellation(DCC)technique with less penalty.
Using Technology Computer-Aided Design(TCAD) 3-D simulation,the single event effect(SEE) of 25 nm raised source-drain FinFET is studied.Based on the calibrated 3-D models by process simulation,it is found that the amount of charge collected increases linearly as the linear energy transfer(LET) increases for both n-type and p-type FinFET hits,but the single event transient(SET) pulse width is not linear with the incidence LET and the increasing rate will gradually reduce as the LET increases.The impacts of wafer thickness on the charge collection are also analyzed,and it is shown that a larger thickness can bring about stronger charge collection.Thus reducing the wafer thickness could mitigate the SET effect for FinFET technology.
