通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)和多值存储原理的研究,提出一种基于CNFET的单端口三值SRAM设计方案。该方案首先利用碳纳米管的多阈值特性设计三值反相器,并采用交叉耦合方式实现三值数据的存储;其次结合读写共用的单端口方法,减少互连线数量;然后采用隔离和切断交叉耦合技术,增强三值数据存储的稳定性;最后通过HSPICE仿真,结果表明所设计的电路逻辑功能正确,且与传统CMOS设计的三值SRAM相比读写速度提高24%。
Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.
A design of a replica bit line control circuit to optimize power for SRAM is proposed. The proposed design overcomes the limitations of the traditional replica bit line control circuit, which cannot shut off the word line in time. In the novel design, the delay of word line enable and disable paths are balanced. Thus, the word line can be opened and shut off in time. Moreover, the chip select signal is decomposed, which prevents feedback oscillations caused by the replica bit line and the replica word line. As a result, the switch power caused by unnec- essary discharging of the bit line is reduced. A 2-kb SRAM is fully custom designed in an SMIC 65-nm CMOS process. The traditional replica bit line control circuit and the new replica bit line control circuit are used in the designed SRAM, and their performances are compared with each other. The experimental results show that at a supply voltage of 1.2 V, the switch power consumption of the memory array can be reduced by 53.7%.
A metastability-based TRNG（true random number generator） is presented in this paper, and implemented in FPGA. The metastable state of a D flip-flop is tunable through a two-stage PDL（programmable delay line）.With the proposed coarse-tuning PDL structure, the TRNG core does not require extra placement and routing to ensure its entropy. Furthermore, the core needs fewer stages of coarse-tuning PDL at higher operating frequency,and thus saves more resources in FPGA. The designed TRNG achieves 25 Mbps @ 100 MHz throughput after proper post-processing, which is several times higher than other previous TRNGs based on FPGA. Moreover, the robustness of the system is enhanced with the adoption of a feedback system. The quality of the designed TRNG is verified by NIST（National Institute of Standards and Technology） and also accepted by class P1 of the AIS-20/31 test suite.
A power balance static random-access memory（SRAM） for resistance to differential power analysis（DPA） is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional shortcircuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm^2.The post-simulation results show that the normalized energy deviation（NED） and normalized standard deviation（NSD） are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.
By researching the ternary counter and low power circuit design method, a novel design of low power ternary Domino counter on switch-level is proposed. Firstly, the switch-level structure expression of ternary loop operation circuit with enable pin is derived according to the switch-signal theory, and the one bit ternary counter is obtained combining the ternary adiabatic Domino literal operation circuit and buffer. Then the switch-level structure expression of enable signal circuit is derived, and the four bits ternary counter is obtained by cascade connection. Finally, the circuit is simulated by Spice tool and the output waveforms transform in proper order indicating that the logic function is correct. The energy consumption of the four bits ternary adiabatic Domino counter is 63% less than the conventional Domino counterpart.
