A 30Gbit/s receptor module is developed with a CMOS integrated receiver chip（IC） and a GaAs-based 1 × 12 photo detector array of PIN-type. Parallel technology is adopted in this module to realize a high-speed receiver module with medium speed devices. A high-speed printed circuit board（PCB） is designed and produced. The IC chip and the PD array are packaged on the PCB by chip-on-board technology. Flip chip alignment is used for the PD array accurately assembled on the module so that a plug-type optical port is built. Test results show that the module can receive parallel signals at 30Gbit/s. The sensitivity of the module is - 13.6dBm for 10^-13 BER.
We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor （MOS） capacitor configuration integrated into silicon-on-insulator （SOl）. Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure, which boosts the modulation efficiency compared with a single MOS capacitor. The simulation results demonstrate that the Vπ Lπ product is 2. 4V · cm. The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve, respectively,indicating a bandwidth of 8GHz. The phase shift efficiency and bandwidth can be enhanced by rib width scaling.
This paper devoted to report the design and the achievement of an optical communication subsystem with 12 parallel channels in one chip.The system is capable of transmitting 10 Gbps bidirectional date over hundreds of meters.It can provide error detection and correction by using 8B/10B encoding and Cyclical Redundancy Checking (CRC) encoding when only single-channel fails.The design scheme has already passed the simulation in FPGA.This technique is useful to enhance the capability and the reliability of the very short reach (VSR) transmission systems.
CHEN Xiong-bin JIA Jiu-chun ZHOU Yi TANG Jun PEI Wei-hua LIU Bo CHEN Hong-da
