在基于数字信号处理的粒子探测器读出电路设计中,模数转化器(analog to digital converter,ADC)是一个关键的模块。ADC的采样率和精度是限制探测系统达到最佳噪声性能的主要参数。基于Matlab的Simulink环境建立了粒子探测器读出电路中ADC的仿真模型,并通过Matlab仿真验证了模数转化器的采样速度、精度对系统噪声的影响,给出了在基于数字信号处理的粒子探测器读出电路设计中,模数转换器的参数设计方案。
This paper presents an AES（advanced encryption standard） chip that combats differential power analysis （DPA） side-channel attack through hardware-based random order execution.Both decryption and encryption procedures of an AES are implemented on the chip.A fine-grained dataflow architecture is proposed,which dynamically exploits intrinsic byte-level independence in the algorithm.A novel circuit called an HMF（Hold-MatchFetch） unit is proposed for random control,which randomly sets execution orders for concurrent operations.The AES chip was manufactured in SMIC 0.18μm technology.The average energy for encrypting one group of plain texts（128 bits secrete keys） is 19 nJ.The core area is 0.43 mm^2.A sophisticated experimental setup was built to test the DPA resistance.Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack.Compared with the corresponding fixed order execution,the hardware based random order execution is improved by at least 21 times the DPA resistance.
A low power and low voltage∑△analog-to-digital modulator is realized with digital CMOS technology, which is due to full compensated depletion mode capacitors.Compared with mixed signal technology,this type of modulator is more compatible for pure digital applications.A pseudo-two-stage class-AB OTA is used in switchedcapacitor integrators for low voltage and low power.The modulator is realized in standard SMIC 0.18μm 1P6M digital CMOS technology.Measured results show that with 1.2 V supply voltage and a 6 MHz sample clock,the dynamic range of the modulator is 84 dB and the total power dissipation is 2460μW.
