A new improved technique,based on the direct current current voltage and charge pumping methods,is proposed for measurements of interface traps density in the channel and the drain region for LDD n MOSFET.This technique can be applied to virgin samples and those subjected to hot carrier stress,and the latter are known to cause the interface damage in the drain region and the channel region.The generation of interface traps density in the channel region and in the drain region can be clearly distinguished by using this technique.
研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。
The saturation behavior of stress current is studied.The three types of precursor sites for trap generation are also introduced by fitting method based on first order rate equation.A further investigation by statistics experiments shows that there are definite relationships among time constant of trap generation,the time to breakdown,and stress voltage.It also means that the time constant of trap generation can be used to predict oxide lifetime.This method is faster for TDDB study compared with usual breakdown experiments.
Gate current for pMOSFETs is composed of direct tunneling current,channel hot hole,electron injection current,and highly energetic hot holes by secondary impact ionization.The device degradation under V g=V d/2 is mainly caused by the injection of hot electrons by primary impact ionization and hot holes by secondary impact ionization,and the device lifetime is assumed to be inversely proportional to the hot holes,which is able to surmount Si-SiO 2 barrier and be injected into the gate oxide.A new lifetime prediction model is proposed on the basis and validated to agree well with the experiment.
The degradation characteristics of both wide and narrow devices under V _g= V _d/2 stress mode is investigated.The width-enhanced device degradation can be seen with devices narrowing.The main degradation mechanism is interface state generation for pMOSFETs with different channel width.The cause of the width-enhanced device degradation is attributed to the combination of width-enhanced threshold voltage and series resistance.
A study of the gate current variation is presented for various thickness ultrathin gate oxides ranging from 1.9 to 3.0nm under the constant voltage stress.The experimental results show the stress induced leakage current(SILC) includes two parts.One is due to the interface trap-assisted tunneling.The other is owing to the oxide trap-assisted tunneling.
