Most of users are accustomed to utilizing virtual address in their parallel programs running at the scalable high-performance parallel computing systems.Therefore a virtual and physical address translation mechanism is necessary and crucial to bridge the hardware interface and software application.In this paper,a new virtual and physical translation mechanism is proposed,which includes an address validity checker,an address translation cache(ATC),a complete refresh scheme and many reliability designs.The ATC employs a large capacity embedded dynamic random access memory(eDRAM)to meet the high hit ratio requirement.It also can switch the cache and buffer mode to avoid the high latency of accessing the main memory outside.Many tests have been conducted on the real chip,which implements the address translation mechanism.The results show that the ATC has a high hit ratio while running the well-known benchmarks,and additionally demonstrates that the new high-performance mechanism is well designed.
