A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18μm CMOS. An opamp- sharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique. The ADC achieves a peak SNDR of 60.1 dB （ENOB = 9.69 bits） and a peak SFDR of 76 dB, while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth. The core area of the ADC is 1.1 mm2 and the chip consumes 28 mW with a 1.8 V power supply.
This paper presents a 25-MHz fully-integrated digitally controlled crystal oscillator（DCXO） with automatic amplitude control（AAC）.The DCXO is based on Colpitts topology for one-pin solution.The AAC circuit is introduced to optimize the phase noise performance.The automatic frequency control is realized by a 10-bit thermometer-code segmental tapered MOS capacitor array,ensuring a～35 ppm tuning range and～0.04 ppm frequency step.The measured phase noise results are-139 dBc/Hz at 1 kHz and-151 dBc/Hz at 10 kHz frequency offset,respectively.The chip consumes 1 mA at 1.8V supply and occupies 0.4 mm^2 in a 0.18-μm CMOS process.
This paper describes the design of a fractional-N frequency synthesizer for digital video broadcasting-terrestrial （DVB-T） receivers.Transfer functions in differentially-tuned PLL are derived and loop parameters are designed. In addition,a fully-differential charge pump is presented.An 8/9 high speed prescaler is analyzed and the design considerations for the CML logic are also presented.Test results show that the RMS phase error is less than 0.7°in integer-N mode and less than 1°in fractional-N mode.The implemented frequency synthesizer draws 10 mA from a 1.8-V supply while occupying a die area of about 1-mm^2 in a 0.18-μm CMOS process.
A fully-differential charge pump（FDCP）with perfect current matching and low output current noise is realized for phase-locked loops（PLLs）.An easily stable common-mode feedback（CMFB）circuit which can handle high input voltage swing is proposed.Current mismatch and current noise contribution from the CMFB circuit is minimized.In order to optimize PLL phase noise,the output current noise of the FDCP is analyzed in detail and calculated with the sampling principle.The calculation result agrees well with the simulation.Based on the noise analysis,many methods to lower output current noise of the FDCP are discussed.The fully-differential charge pump is integrated into a 1–2 GHz frequency synthesizer and fabricated in an SMIC CMOS 0.18μm process.The measured output reference spur is–64 dBc to–69 dBc.The in-band and out-band phase noise is–95 dBc/Hz at 3 kHz frequency offset and–123 dBc/Hz at 1 MHz frequency offset respectively.
