基于开关电容阵列(SCA)技术可以实现超高速的波形数字化。本研究是基于实验室设计完成的FEL SCA芯片进行8通道2 Gsps的波形数字化模块的设计,电路的配置和读出控制功能集成在单个FPGA中完成,此外该模块还包含SDRAM缓存及USB接口。目前已在实验室环境下对其进行了直流电压测试、瞬态波形测试和带宽测试,测试结果表明,在FEL SCA芯片的输入动态范围100 m V～1 V之间,本波形数字化模块的INL好于1%,通道的RMS噪声约为1.76 m V,带宽约为450 MHz,达到设计目标。
A trigger system was designed for the external target experiment in the Cooling Storage Ring （CSR） of the Heavy Ion Research Facility in Lanzhou （HIRFL）. Considering that different detectors are scattered over a large area, the trigger system is designed based on a master-slave structure and fiber-based serial data transmission technique. The trigger logic is organized in hierarchies, and flexible reconfiguration of the trigger function is achieved based on command register access or overall field-programmable gate array （FPGA） logic on-line reconfiguration controlled by remote computers. We also conducted tests to confirm the function of the trigger electronics, and the results indicate that this trigger system works well.
High precision time measurement is required in the readout of the neutron wall and TOF walls in the external target experiment of the Cooling Storage Ring(CSR) project in the Heavy Ion Research Facility in Lanzhou(HIRFL).Considering the time walk correction,both time and charge are measured in the readout electronics.In this 16-channel measurement module,time and charge information are digitized by TDCs at the same time based on the Time-Over-Threshold(TOT) method;meanwhile,by employing high-density ASIC chips,the electronics complexity is effectively reduced.Test results indicate that this module achieves a time resolution better than 25 ps and a charge resolution better than 5%over the input amplitude range from 50 mV to 3V.
Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays（FPGAs）, FPGA time-to-digital converters（TDCs） have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold（TOT） measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC＇s integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.
