This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors. The SRAM cell is based on 32nm silicon-on-insulator （SO1） technology node. It consists of two access transistors and two pull-down transistors. The pull-down transistors have larger channel length than the access transistors. Due to the significant short channel effect of small-size MOS transistors, the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic ＂1＂ while in standby. The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable ＂read＂ operation of the cell. The use of back-gate feedback also helps to im- prove the static noise margin （SNM） of the cell. The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells. The speed and power dissipation of the SRAM cell are simulated and discussed. The SRAM cell can operate with a 0. 5V supply voltage.
This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc.
This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier（LNA）circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.
This paper proposes a novel single electron random number generator （RNG）. The generator consists of multiple tunneling junctions （MTJ） and a hybrid single electron transistor （SET）/MOS output circuit. It is an oscillator-based RNG. MTJ is used to implement a high-frequency oscillator, which uses the inherent physical randomness in tunneling events of the MTJ to achieve large frequency drift. The hybrid SET and MOS output circuit is used to amplify and buffer the output signal of the MTJ oscillator. The RNG circuit generates high-quality random digital sequences with a simple structure. The operation speed of this circuit is as high as 1GHz. The circuit also has good driven capability and low power dissipation. This novel random number generator is a promising device for future cryptographic systems and communication applications.
