Repeater optimization is the key for SOC （System on Chip） interconnect delay design. This paper proposes a novel optimal model for minimizing power and area overhead of repeaters while meeting the target performance of on-chip interconnect lines. It also presents Lagrangian function to find the number of repeaters and their sizes required for minimizing area and power overhead with target delay constraint. Based on the 65 nanometre CMOS technology, the computed results of the intermediate and global lines show that the proposed model can significantly reduce area and power of interconnected lines, and the better performance will be achieved with the longer line. The results compared with the reference paper demonstrate the validity of this model. It can be integrated into repeater design methodology and CAD （computer aided design） tool for interconnect planning in nanometre SOC.
A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.
Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor （CMOS） process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design （CAD） of very large-scale integrated circuits （VLSIs） in nano-scale technologies.
This paper proposes a new optimization method to improve the performance of a null convention logic asynchronous pipeline.Parallel combinational logic modules in the pipelines can work alternately in null and data cycles by using a parallel processing mode.The complete waiting time for both null and data signals of combinational logic output in previous asynchronous register stage is reduced by decoupling the output from combinational logic modules.Performance penalty brought by null cycle is reduced while the data processing capacity is increased.The novel asynchronous pipeline based on asynchronous full adders with different bit widths as asynchronous combination logic modules is simulated using 0.18-μm CMOS technology.Based on 6 bits asynchronous adder as asynchronous combination logic modules, the simulation result of this new pipeline proposal demonstrates a high throughput up to 72.4% improvement with appropriate power consumption.This indicates the new design proposal is preferable for high-speed as ynchronous designs due to its high throughput and delay-insensitivity.
Based on the SinoMOS 1 μm 40 V CMOS process, a novel power factor corrention （PFC） converter with a low-power variable frequency function is presented. The circuit introduces a multi-vector error amplifier and a programmable oscillator to achieve frequency modulation, which provides a rapid dynamic response and precise output voltage clamping with low power in the entire load. According to the external load variation, the system can modulate the circuit operating frequency linearly, thereby ensuring that the PFC converter can work in frequency conversionmode. Measured results show that the normal operating frequency of the PFC converter is 5-6 kHz, the start-up current is 36 μA, the stable operating current is only 2.43 mA, the efficiency is 97.3%, the power factor （PF） is 0.988, THD is 3.8%, the load adjust rate is 3%, and the linear adjust rate is less than 1%. Both theoretical and practical results reveal that the power consumption of the whole supply system is reduced efficiently, especially when the load varies. The active die area of the PFC converter chip is 1.61 ×1.52 mm^2.
Large transmission power consumptions and excessive interconnection lines are two shortcomings which exist in conventional network-on-chips. To improve performance in these areas, this paper proposes a full asynchronous serial transmission converter for network-on-chips. By grouping the parallel data between routers into smaller data blocks, interconnection lines between routers can be greatly reduced, which finally brings about saving of power over- heads in the transmission process. Null convention logic units are used to make the circuit quasi-delay insensitive and highly robust. The proposed serial transmission converter and serial channel are implemented based on SMIC 0.18 μm standard CMOS technology. Results demonstrate that this full asynchronous serial transmission converter can save up to three quarters of the interconnection line resources and also reduce up to two-thirds of the power consumption under 32 bit data widths. The proposed full asynchronous serial transmission converter can apply to the on chip network which is sensitive to area and power.
