As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.
