An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process.The circuit comprises a 3rd-order active-RC complex filter（CF） and a programmable gain amplifier（PGA）.An automatic tuning circuit is also designed to tune the CF＇s pass band.Instead of the class-A fully differential operational amplifier（FDOPA） adopted in the conventional CF and PGA design,a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption.In the PGA circuit,a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly.A reformative switching network is proposed,which can eliminate the switch resistor＇s influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10-50 dB with a 1-dB step size,and the gain accuracy is less than ±0.3 dB.The OIP3 is 23.3 dBm at the gain of 10 dB.Simulation results show that the settling time is reduced from 100 to 1 ms.The image band rejection is about 40 dB.It only draws 4.5 mA current from a 1.8 V supply voltage.
A low-jitter RF phase locked loop（PLL） frequency synthesizer with high-speed mixed-signal down-scaling circuits is proposed.Several techniques are proposed to reduce the design complexity and improve the performance of the mixed-signal down-scaling circuit in the PLL.An improved D-latch is proposed to increase the speed and the driving capability of the DMP in the down-scaling circuit.Through integrating the D-latch with ＇OR＇ logic for dual-modulus operation,the delays associated with both the ＇OR＇ and D-flip-flop（DFF） operations are reduced,and the complexity of the circuit is also decreased.The programmable frequency divider of the down-scaling circuit is realized in a new method based on deep submicron CMOS technology standard cells and a more accurate wire-load model.The charge pump in the PLL is also realized with a novel architecture to improve the current matching characteristic so as to reduce the jitter of the system.The proposed RF PLL frequency synthesizer is realized with a TSMC 0.18-μm CMOS process. The measured phase noise of the PLL frequency synthesizer output at 100 kHz offset from the center frequency is only -101.52 dBc/Hz.The circuit exhibits a low RMS jitter of 3.3 ps.The power consumption of the PLL frequency synthesizer is also as low as 36 mW at a 1.8 V power supply.
In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.
本文根据数据恢复时,本地时钟与输入数据之间的相位关系及其实现方式的不同,将高速时钟与数据恢复(CDR,Clock and Data Recovery)电路技术分为三类,也即前馈相位跟踪型,反馈相位跟踪型,以及盲过采样型。进而又分别对每一类型进行了细分并分别进行了深入的剖析和比较。最后又给出了不同应用环境下,CDR技术的选择策略,并指出了CDR技术的发展趋势。本文通过对高速CDR技术详尽而又深刻的分析比较,勾勒出了一个高速CDR技术的关系及发展演化图,使读者能够对现存的高速CDR技术及其发展趋势有一个前面而又清晰的认识。
A 37. 5 MHz differential complementary metal oxide semiconductor （CMOS） crystal oscillator with low power and low phase noise for the radio frequency tuner of digital radio broadcasting digital radio mondiale （DRAM） and digital audio broadcasting （DAB） systems is realized and characterized. The conventional cross-coupled n-type metal oxide semiconductor （NMOS） transistors are replaced by p-type metal oxide semiconductor （PMOS） transistors to decrease the phase noise in the core part of the crystal oscillator. A symmetry structure of the current mirror is adopted to increase the stability of direct current. The amplitude detecting circuit made up of a single- stage CMOS operational transconductance amplifier （OTA） and a simple amplitude detector is used to improve the current accuracy of the output signals. The chip is fabricated in a 0. 18- pxn CMOS process, and the total chip size is 0. 35 mm x 0. 3 mm. Under a supply voltage of 1.8 V, the measured power consumption is 3.6 mW including the output buffer for 50 testing loads. The proposed crystal oscillator exhibits a low phase noise of - 134. 7 dBc/Hz at 1-kHz offset from the center frequency of 37. 5 MHz.
A high-speed mixed-signal down-scaling circuit with low power consumption and low phase noise for use in digital audio broadcasting tuners has been realized and characterized. Some new circuit techniques are adopted to improve its performance. A dual-modulus prescaler （DMP） with low phase noise is realized with a kind of improved source-coupled logic （SCL） D-flip-flop （DFF） in the synchronous divider and a kind of improved complementary metal oxide semiconductor master-slave （CMOS MS）-DFF in the asynchronous divider. A new more accurate wire-load model is used to realize the pulse-swallow counter （PS counter）. Fabricated in a 0.18-#m CMOS process, the total chip size is 0.6× 0.2 mm2. The DMP in the proposed down-scaling circuit exhibits a low phase noise of-118.2 dBc/Hz at 10 kHz off the carrier frequency. At a supply voltage of 1.8 V, the power consumption of the down-scaling circuit＇s core part is only 2.7 mW.
A complementary metal oxide semiconductor （CMOS） voltage controlled ring oscillator for ultra high frequency （UHF） radio frequency identification （RFID） readers has been realized and characterized. Fabricated in charter 0.35 p.m CMOS process, the total chip size is 0.47 × 0.67 mm^2. While excluding the pads, the core area is only 0.15 ×0.2 mm^2. At a supply voltage of 3.3 V, the measured power consumption is 66 mW including the output buffer for 50 Ω testing load. This proposed voltage-controlled ring oscillator exhibits a low phase noise of - 116 dBc/Hz at 10 MHz offset from the center frequency of 922.5 MHz and a lower tuning gain through the use of coarse/fine frequency control.
