A novel partial silicon-on-insulator laterally double-diffused metal–oxide–semiconductor transistor(PSOI LDMOS)with a thin buried oxide layer is proposed in this paper. The key structure feature of the device is an n+-layer, which is partially buried on the bottom interface of the top silicon layer(PBNL PSOI LDMOS). The undepleted interface n+-layer leads to plenty of positive charges accumulated on the interface, which will modulate the distributions of the lateral and vertical electric fields for the device, resulting in a high breakdown voltage(BV). With the same thickness values of the top silicon layer(10 μm) and buried oxide layer(0.375 μm), the BV of the PBNL PSOI LDMOS increases to 432 V from285 V of the conventional PSOI LDMOS, which is improved by 51.6%.
详细研究了一种基于薄埋氧层及三层顶层硅衬底(Triple-Layer Top Silicon,TLTS)的SOI高压LDMOS器件。该结构在SOI介质层上界面的顶层硅内引入一高浓度n+层,当器件处于反向阻断状态时,高浓度n+区部分耗尽,漏端界面处已耗尽n+层内的高浓度电离施主正电荷可增强介质层电场,所产生的附加电场将调制漂移区内的电场,防止器件在漏端界面处被提前击穿,从而可在较薄的埋氧层(BOX)上获得较高耐压。在0.4μm BOX上获得了624V的耐压。与几种SOI器件相比,所提出的TLTS LDMOS器件具有较高优值(FOM)。
